Longevity Framework: Leveraging Online Integrated Aging-Aware Hierarchical Mapping and VF-Selection for Lifetime Reliability Optimization in Manycore Processors

Rapid device aging in the nano era threatens system lifetime reliability, posing a major intrinsic threat to functionality. Traditional techniques overcome aging-induced slowdown, such as guardbanding are static and incur performance, power, area penalties. In manycore processor, system-level design abstraction offers dynamic opportunities through control of task-to-core mappings per-core operation frequency towards more balanced core profile across chip, optimizing reliability while meeting application performance requirements. This article presents Longevity Framework (LF) that leverages online integrated aging-aware hierarchical mapping voltage (VF)-selection for optimization processors. The exploration is achieve scalability. VF-selection builds on trade-offs involved between VF scaled leveraging DVFS capabilities. methodology takes chip-wide process variation into account. Extensive experimentation, comparing proposed approach with two state-of-the-art methods, 64-core 256-core systems running applications from PARSEC SPLASH-2 benchmark suites, show an improvement up 3.2 years 4× average health.